1. Field of the Invention
Exemplary embodiments of the present invention relate to a variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer for power- and area-efficient 112 Gb/s optical dual-polarization quadrature phase-shift-keying (DP-QPSK) system.
2. Discussion of the Background
Coherent optical dual-polarization quadrature phase-shift-keying (DP-QPSK) systems with electrical domain dispersion compensation at a wavelength of 1550 nm are being adapted for 112 Gb/s long-haul optical communication links in order to combat chromatic dispersion (CD). FIG. 1 shows a typical block diagram of a 11-Gb/s DP-QPSK coherent optical receiver. The phase information of the received optical signal is converted to two pairs of analog voltage signals and 2× oversampled using four 56 GS/s analog-to-digital converters (ADCs). A digital equalizer subsequent to the ADCs compensates for the channel dispersion. Such a high data rate requires a massive parallelization in the ADC and digital equalizer due to the bandwidth limitation of active components. The tight performance requirements of the ADC necessitates complex and area-hungry calibration circuits to overcome various non idealities caused by mismatch among parallel ADCs and nonlinearities in each ADC. The power consumption of the digital equalizer increases in proportion to its dispersion compensation capability and the level of computational precision. The power and area of the conventional coherent DP-QPSK system have been the major impediments to its adaptation to high-volume applications such as Metro dense wavelength division multiplexing (DWDM) despite its excellent dispersion compensation capability.